An active matrix liquid crystal display (“LCD”) device generally includes a display panel and a drive circuit to drive the display panel. The drive circuit may further include a gate driver for selecting one row of gate lines and a source driver for providing pixel signals through source lines to pixels corresponding to the selected gate lines. A gate driver, generally operating in a mixed-voltage environment, requires circuits for converting different voltage levels used therein.
FIG. 1A is a block diagram of a gate driver 10 in the art. For a XGA/SXGA display system, gate driver 10 may include 256 output channels OUT1 to OUT 256. Gate driver 10 includes an input level shifter 12, shift registers 14, control units 16, output level shifters 18, and output buffers 20. Input level shifter 12 converts voltage levels of input signals from an LCD control application specific integrated circuit (“ASIC”). The input signals include control signals such as a left/right shift control signal LR, an output enable signal OE and a global-on control signal XON, a clock signal SCLK, and data signals such as right data input/output DIOR and left data input/output DIOL. Shift registers 14 shift start pulses of signals DIOR or DIOL according to signal LR at a rising edge of signal SCLK. Control units 16 decode signals from shift registers 14 and control operation modes of gate driver 10 through signals OE and XON. Output level shifters 18 convert voltage levels of signals from control units 16. The level-converted signals are stored in output buffers 20 for driving a display panel.
FIG. 1B is a diagram of the different voltage levels used in gate driver 10. The input signals from an LCD control ASIC have a first voltage level ranging from VSS to VDD, for example, 0 volt (V) and 3.6V, respectively. Input level shifter 12 converts the first voltage level to a second voltage level ranging from VEE to VAA, for example, −10V and (−10+(3.6˜5)) V, respectively. The second voltage level is used in input level shifter 12, shift registers 14 and control units 16. Output level shifters 18 convert the second voltage level to a third voltage level ranging from VEE to VCOM, for example, −10V and 25V, respectively. The third voltage level is used in output level shifters 18 and output buffers 20.
An example of output level shifters in the art is disclosed in U.S. patent application Publication No. 20020135555 (hereinafter the '555 application), entitled “Single-Ended High-Voltage Level Shifter for a TFT-LCD Gate Driver”. Specifically, in FIG. 5 of the '555 application, a 2-level output level shifter 51 is disclosed. Level shifter 51 includes two high-voltage transistors M1 and M2 for converting voltage levels of an input signal. By incorporating a partial circuitry 511, level shifter 51 reduces chip area. However, partial circuitry 51 includes two other high-voltage transistors M11 and M12 operating in response to global-on control signals XON2 and XON3 to prevent level shifter 51 from large static power consumption. Furthermore, additional level shifters are required to generate voltage levels for the signals XON2 and XON3. As a result, level shifter 51 may disadvantageously become complicated and still occupy a large chip area.